專用集成電路：英文版

定　價：￥86.00

作　者：	（美）Michael John Sebastian Smith著
出版社：	電子工業(yè)出版社
叢編項：	國外電子與通信教材系列
標　簽：	集成電路

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ISBN：	9787505384071	出版時間：	2003-01-01	包裝：	膠版紙
開本：	24cm	頁數(shù)：	1024	字數(shù)：

內(nèi)容簡介

　　本書是一本有關專用集成電路（ASIC）的綜合性和權(quán)威性書籍。書中敘述了VLSI系統(tǒng)設計的最新方法。利用商業(yè)化工具以及預先設計好的單元庫已使得ASIC設計成為速度最快、成本最低而且錯誤最少的一種IC設計方法，因而ASIC和ASIC設計方法已迅速在工業(yè)界的各個應用領域得到推廣。本書介紹了半定制和可編程的ASIC。在對每種ASIC類型的數(shù)字邏輯設計與物理特性的基本原理進行描述后，討論了ASIC邏輯設計——設計輸入、邏輯綜合、仿真以及測試，并進一步講述了相應的物理設計——劃分、平面布圖規(guī)劃、布局以及布線。此外，本書對在ASIC設計中需要了解的各方面知識以及必需的工作都有詳盡敘述。本書可作為大學高年級和研究生教材，也是ASIC領域工程技術(shù)人員的理想?yún)⒖紩?/div>

作者簡介

　　MichaelJohnSebastianSmith是一位ASIC領域的研究者、設計者和教育工作者。他任教于夏威夷大學，同時又是ASIC的設計顧問。他曾在IBMT.J.Watson研究中心工作，是CompassDesignAutomation公司的創(chuàng)辦人之一，該公司目前是Avant！公司的一部分。Smith曾在劍橋大學皇后學院獲得文學學士和文學碩士學位，并在斯坦福大學獲得理科碩士和博士學位。1989年被授予美國國家科學基金總統(tǒng)青年研究者稱號。

圖書目錄

1 INTRODUCTION TO ASICs 1
      1 .1 Types of ASICs 4
      1 .2 Design Flow 16
      1 .3 Case Study 18
      1 .4 Economics of ASICs 20
      1 .5 ASIC Cell Libraries 27
      1 .6 Summary 30
      1 .7 Problems 31
      1 .8 Bibliography 36
      1 .9 References 38
2 CMOS LOGIC 39
      2.1 CMOS Transistors 41
      2.2 The CMOS Process 49
      2.3 CMOS Design Rules 58
      2.4 Combinational Logic Cells 60
      2.5 Sequential Logic Cells 70
      2.6 Datapath Logic Cells 75
      2.7 I/O Cells 99
      2.8 Cell Compilers 102
      2.9 Summary 102
      2.10 Problems 103
      2.11 Bibliography 113
      2.12 References 1 14
3 ASIC LIBRARY DESIGN 117
      3.1 Transistors as Resistors 117
      3.2 Transistor Parasitic Capacitance 122
      3.3 Logical Effort 129
      9.4 Library-Cell Design 141
      9.5 Library Architecture 142
      3.6 Gate-Array Design 144
      3.7 Standard-Cell Design 150
      3.8 Datapath-Cell Design 152
      3.9 Summary 155
      3.10 Problems 155
      3.11 Bibliography 187
      3.12 References 168
      4 PROGRAMMABLE ASICs 169
      4.1 The Antifuse 170
      4.2 Static RAM 1 74
      4.3 EPROM and EEPROM Technology 174
      4.4 Praaical Isues 1 7e
      4.5 Specifications 1 7B
      4.6 PREP Benchmarks 1 79
      4.7 FPGA Economics 1 80
      4.8 Summary 184
      4.9 Problems 185
      4.10 Bibliography 190
      4.11 References 190
5 PROGRAMMABLE ASIC
      LOGIC CELLS 191
      5.1 Actel ACT 191
      5.2 Xilinx LCA 204
      5.3 Altera FLEX 209
      5.4 Altera MAX 209
      5.5 Summary 218
      5.6 Problems 224
      5.7 Bibliography 229
      5.8 References 230
6 PROGRAMMABLE
      ASIC I/O CELLS 231
      6.1 Dc Output 292
      6.2 AC Output 295
      8.9 DC Input 243
      6.4 AC Input 24B
      6.5 Clock Input 253
      6.6 Power Input 255
      6.7 Xilinx I/O Block 258
      6.8 Other I/O Cells 261
      6.9 Summary 262
      e.10 Problems 269
      6.11 Bibliography 272
      6.12 References 273
7 PROGRAMMABLE
      ASIC INTERCONNECT 275
      7.1 Aael ACT 275
      7.2 Xilinx LCA 284
      7.S Xilinx EPLD 288
      7.4 Altera MAX 5000 and 7000 289
      7.5 Altera MAX 9000 290
      7.6 Altera FLEX 291
      7.7 Summary 292
      7.8 Problems 294
      7.9 Bibliography 297
      7.10 References 297
8 PROGRAMMABLE
      ASIC DESIGN SOFTWARE 299
      8.1 Desian Svstems 299
      8.2 Logic Synthesis 3O4
      8.3 The Halfgate ASIC 307
      8.4 Summary 316
      8.5 Probiems 316
      8.6 Bibliography 320
      8.7 References 326
      9 LOW-LEVEL
      DESIGN ENTRY 327
9.1 Schematic Entry 328
      9.2 Low-Level Design Languages 345
      9.3 PLA Tools 353
      9.4 EDIF 355
      9.5 CFI Design Representation 969
      9.6 Summary 373
      9.7 Problems 373
      9.8 Bibliography 376
      9.9 References 377
10 VHDL 379
     10.1 A Counter 38O
     10.2 A 4-bit Multiplier 381
     10.3 Syntax and Semantics of VHDL 390
     10.4 Identifiers and Literals 392
     10.5 Entities and Architectures 393
     10.6 Packages and Libraries 398
     10. 7  Interface DecIarations 405
     10. 8  Type DecIartions  411
     10. 9  Other Declarations 413
     10. 10  Sequential Statements 419
     10. 11  Operators 430
     10. 12  Arithmetic 432
     10. 13  Concurrent Statements 437
     10. 14  Execution 445
     10. 15  Configurations and Specifications 447
     10. 16  An Engine Controller 449
     10. 17  Summary 456
     10. 18  Problems 459
     10. 19  Bibliography 477
     10. 20  References 478
11  VERlLOG HDL 479
     11. 1 ACounter 480
     11. 2 Basics of  the Verilog Language 482
     11. 3 Operators 490
     11. 4 Hierchy 494
     11. 5 Procedures and Assignments 495
     11. 6 Timing ControIs and DeIay 498
     11. 7 Tasks and Functions 506
     11. 8 COntrol Statements 506
     11. 9  LogiC-Gate Modding 509
     11. 10  ModeIing Delay 512
     11. 11  AItering Parameters 515
     11. 12  A Viterbi  Decoder 515
     11. 13  Other Verilog Features 532
     11. 14  Summary 541
     11. 15  ProbIems 543
     11. 16  Bibliography 557
     11. 17  References 557
12  LOGIC SYNTHESIS 559
     12. 1    A Logic-Synthesis ExampIe 560
     12. 2    A Comparator／MUX 561
     12. 3    Inside a Logic Synthesizer 569
     12. 4    Synthesis of the Viterbi Decoder 572
     12. 5    Verilog and Logic Synthesis 580
     12. 6    VHDL and Loqic Synthesis 593
     12. 7    Finite—State Machine Synthesis  605
     12. 8    Memory Synthesis  611
     12. 9    The MuItiplier  614
     12. 10  The Engine Controller 619
     12. 11  Performance-Driven Synthesis 620
     12. 12  Optimization of the Viterbi Decoder 625
     12. 13  Summary 628
     12. 14  ProbIems 629
     12. 15  BibIiography 638
     12. 16  References 639
13  SIMULATION 641
     13. 1  Types of SimuIation 641
     13. 2  The Comparator／MUX ExampIe 643
     13. 3  Logic SyStems 652
     13. 4  How Logic SimuIation Works  656
     13. 5  Cell ModeIs 659
     13. 6  Delay Models 669
     13. 7    Static Timing AnaIysis 675
     13. 8    Formal Verification 682
     13. 9  SwitCh-Level Simulation 688
     13. 10  Transistor—LeveI SimuIation 689
     13. 11  Summary 696
     13. 12  ProbIems 696
     13. 13  Bibliography 708
     13. 14  Referellces 708
14  TEST 711
     14. 1  The Lmportance of Test 712
     14. 2  Boundary-Scan Test 714
     14. 3  FauIts 736
     14. 4  FauIt SimuIation 745
     14. 5  Automatic Test-Pattern Generation 755
     14. 6  Scan Test 764
     14. 7  Built—in SeIf—test 766
     14. 8  A SimpIe Test Example 778
     14. 9  The Viterbi Decoder Example 791
     14. 10  Summary 794
     14. 11  Problems 794
     14. 12  BibIiography 800
     14. 13  References 801
15  ASIC CONSTRUCTION 805
     15. 1  PhySiCal Design 805
     15. 2  CAD Tools 807
     15. 3  System Partitioning 809
     15. 4  Estimating ASIC Size 811
     15. 5  Power Dissipation  816
     15. 6  FPGA Partitioning 820
     15. 7  Partitioning Methods 824
     15. 8  Summary 838
     15. 9  ProbIems 838
     15. 10  BibIiography 850
     15. 11  References 851
16  FLOORPLANNlNG
     AND PLACEMENT 853
     16. 1    Floorplanning 853
     16. 2    PIacement 873
     16. 3    Physical Design Flow 894
     16. 4    Information Formats 895
     16. 5    Summary 898
     16. 6    ProbIems 898
     16. 7    BibIiography 906
     16. 8    References 906
17  ROUTlNG 909
     17. 1    GIobal Routing 910
     17. 2    Detailed Routing 922
     17. 3    Special Routing 935
     17. 4    Circuit Extraction and DRC 939
      17.5 Summary 946
      1 7.6 Problems 947
      1 7.7 Bibliography 956
      1 7.8 References 957
A VHDL RESOURCES 961
      1.1 BNF 961
      1 .2 VHDL Syntax 963
      1 .3 BNF Index 979
      1 .4 Bibliography 973
      1 .5 References 976
B VERILOG HDL
      RESOURCES 979
      2.1 Explanation of the Verilog HDL BNF 979
      2.2 Verilog HDL Syntax 980
      2.3 BNF Index 994
      2.4 Verilog HDL LRM 994
      2.5 Bibliography 997
      2.6 References 999
      GLOSSARY 1000
      INDEX 1006